Álmos Veres-Vitályos

Programming Digilent FPGA Boards with Multisim

This guide will provide a step by step tutorial of how to add an FPGA board to Multisim and how to create and upload a PLD design to it.

Programming Digilent FPGA Boards with Multisim

Things used in this project

Hardware components

Arty S7-50
Digilent Arty S7-50
or any other Digilent FPGA board of your choice

Software apps and online services

NI Multisim Desktop
Education version 14.2, or higher
Vivado Design Suite HLx Editions
Xilinx Vivado Design Suite HLx Editions
VS Code
Microsoft VS Code
or any other editor of your choice
Digilent Adept


Read more


Test Design

The test design: switches connected to LEDs through buffers.



Plain text
The final (edited) constraints file, specific to my project
## This file is a general .xdc for the Arty S7-50 Rev. E
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock Signals
set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { CLK12MHZ }]; #IO_L13P_T2_MRCC_15 Sch=uclk
#create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { CLK12MHZ }];
set_property -dict { PACKAGE_PIN R2    IOSTANDARD SSTL135 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000}  [get_ports { CLK100MHZ }];

## Switches
set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { sw0 }]; #IO_L20N_T3_A19_15 Sch=sw0
set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { sw1 }]; #IO_L21P_T3_DQS_15 Sch=sw1
set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { sw2 }]; #IO_L21N_T3_DQS_A18_15 Sch=sw2
set_property -dict { PACKAGE_PIN M5    IOSTANDARD SSTL135 } [get_ports { sw3 }]; #IO_L6N_T0_VREF_34 Sch=sw3

set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L16P_T2_A28_15 Sch=led1_g
set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b

## LEDs
set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { led0 }]; #IO_L16N_T2_A27_15 Sch=led2
set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { led1 }]; #IO_L17P_T2_A26_15 Sch=led3
set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS33 } [get_ports { led2 }]; #IO_L17N_T2_A25_15 Sch=led4
set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { led3 }]; #IO_L18P_T2_A24_15 Sch=led5

## Buttons
set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L18N_T2_A23_15 Sch=btn0
set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { btn1 }]; #IO_L19P_T3_A22_15 Sch=btn1
set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { btn2 }]; #IO_L19N_T3_A21_VREF_15 Sch=btn2
set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVCMOS33 } [get_ports { btn3 }]; #IO_L20P_T3_A20_15 Sch=btn3

## Pmod Header JA
set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ja0 }]; #IO_L4P_T0_D04_14 Sch=ja_p1
set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja1 }]; #IO_L4N_T0_D05_14 Sch=ja_n1
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { ja2 }]; #IO_L5P_T0_D06_14 Sch=ja_p2
set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ja3 }]; #IO_L5N_T0_D07_14 Sch=ja_n2
set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ja4 }]; #IO_L7P_T1_D09_14 Sch=ja_p3
set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ja5 }]; #IO_L7N_T1_D10_14 Sch=ja_n3
set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ja6 }]; #IO_L8P_T1_D11_14 Sch=ja_p4
set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja7 }]; #IO_L8N_T1_D12_14 Sch=ja_n4

## Pmod Header JB
set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { jb0 }]; #IO_L9P_T1_DQS_14 Sch=jb_p1
set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { jb1 }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n1
set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { jb2 }]; #IO_L10P_T1_D14_14 Sch=jb_p2
set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { jb3 }]; #IO_L10N_T1_D15_14 Sch=jb_n2
set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { jb4 }]; #IO_L11P_T1_SRCC_14 Sch=jb_p3
set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { jb5 }]; #IO_L11N_T1_SRCC_14 Sch=jb_n3
set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { jb6 }]; #IO_L12P_T1_MRCC_14 Sch=jb_p4
set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { jb7 }]; #IO_L12N_T1_MRCC_14 Sch=jb_n4

## Pmod Header JC
set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { jc0 }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { jc1 }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { jc2 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { jc3 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { jc4 }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
set_property -dict { PACKAGE_PIN P13   IOSTANDARD LVCMOS33 } [get_ports { jc5 }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { jc6 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc7 }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]

## Pmod Header JD
set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { jd0 }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jd1 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { jd2 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { jd3 }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jd4 }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { jd5 }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jd6 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { jd7 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]

## USB-UART Interface
set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in

## ChipKit Outer Digital Header
set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_0_14 Sch=ck_io0
set_property -dict { PACKAGE_PIN N13   IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L6N_T0_D08_VREF_14   Sch=ck_io1
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=ck_io2
set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L13P_T2_MRCC_14      Sch=ck_io3
set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L13N_T2_MRCC_14      Sch=ck_io4
set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14      Sch=ck_io5
set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14      Sch=ck_io6
set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L16N_T2_A15_D31_14   Sch=ck_io7
set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L17P_T2_A14_D30_14   Sch=ck_io8
set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L17N_T2_A13_D29_14   Sch=ck_io9

## ChipKit SPI Header
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss   }]; #IO_L22P_T3_A17_15   Sch=ck_io10_ss
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15   Sch=ck_io11_mosi
set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck  }]; #IO_L14P_T2_SRCC_15  Sch=ck_io13_sck

## ChipKit Inner Digital Header
## Note: these pins are shared with PMOD Headers JC and JD and cannot be used at the same time as the applicable PMOD interface(s)
#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L24P_T3_A01_D17_14        Sch=jd10/ck_io[26]
#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L23N_T3_A02_D18_14        Sch=jd9/ck_io[27]
#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L23P_T3_A03_D19_14        Sch=jd8/ck_io[28]
#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L22N_T3_A04_D20_14        Sch=jd7/ck_io[29]
#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A05_D21_14        Sch=jd4/ck_io[30]
#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L21N_T3_DQS_A06_D22_14    Sch=jd3/ck_io[31]
#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L21P_T3_DQS_14            Sch=jd2/ck_io[32]
#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_A07_D23_14        Sch=jd1/ck_io[33]
#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L20P_T3_A08_D24_14        Sch=jc10/ck_io[34]
#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19N_T3_A09_D25_VREF_14   Sch=jc9/ck_io[35]
#set_property -dict { PACKAGE_PIN P13   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L19P_T3_A10_D26_14        Sch=jc8/ck_io[36]
#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L16P_T2_CSI_B_14          Sch=jc7/ck_io[37]
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L15P_T2_DQS_RDWR_B_14     Sch=jc3/ck_io[39]
#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L18N_T2_A11_D27_14        Sch=jc2/ck_io[40]
#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18P_T2_A12_D28_14        Sch=jc1/ck_io[41]

## Dedicated Analog Inputs
set_property -dict { PACKAGE_PIN J10   } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p
set_property -dict { PACKAGE_PIN K9    } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n

## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
## WARNING: Do not use both sets of constraints at the same time!
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15     Sch=ck_an_p0   ChipKit pin=A0
#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15     Sch=ck_an_n0   ChipKit pin=A0
#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p  }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p1   ChipKit pin=A1
#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n  }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n1   ChipKit pin=A1
#set_property -dict { PACKAGE_PIN E12   IOSTANDARD LVCMOS33 } [get_ports { vaux9_p  }]; #IO_L5P_T0_AD9P_15     Sch=ck_an_p2   ChipKit pin=A2
#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { vaux9_n  }]; #IO_L5N_T0_AD9N_15     Sch=ck_an_n2   ChipKit pin=A2
#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { vaux2_p  }]; #IO_L7P_T1_AD2P_15     Sch=ck_an_p3   ChipKit pin=A3
#set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { vaux2_n  }]; #IO_L7N_T1_AD2N_15     Sch=ck_an_n3   ChipKit pin=A3
#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L8P_T1_AD10P_15    Sch=ck_an_p4   ChipKit pin=A4
#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L8N_T1_AD10N_15    Sch=ck_an_n4   ChipKit pin=A4
#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L10P_T1_AD11P_15   Sch=ck_an_p5   ChipKit pin=A5
#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L10N_T1_AD11N_15   Sch=ck_an_n5   ChipKit pin=A5
## ChipKit Outer Analog Header - as Digital I/O
## NOTE: The following constraints should be used when using these ports as digital I/O.
set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_15            Sch=ck_a0
set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_15       Sch=ck_a1
set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_15       Sch=ck_a2
set_property -dict { PACKAGE_PIN C13   IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_15       Sch=ck_a3
set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_15  Sch=ck_a4
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_15 Sch=ck_a5

## ChipKit Inner Analog Header - as Differential Analog Inputs
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
## WARNING: Do not use both sets of constraints at the same time!
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15     Sch=ad_p8   ChipKit pin=A6
#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15     Sch=ad_n8   ChipKit pin=A7
#set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p3   ChipKit pin=A8
#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n3   ChipKit pin=A9
## ChipKit Inner Analog Header - as Digital I/O
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L2P_T0_AD8P_15     Sch=ad_p8
set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L2N_T0_AD8N_15     Sch=ad_n8
set_property -dict { PACKAGE_PIN D16   IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p3
set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n3
set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L12P_T1_MRCC_15    Sch=ck_a10_r   (Cannot be used as an analog input)
set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L12N_T1_MRCC_15    Sch=ck_a11_r   (Cannot be used as an analog input)

## ChipKit I2C
set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl
set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda

## Misc. ChipKit Ports
set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa
set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L11N_T1_SRCC_15

## Quad SPI Flash
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq0 }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq0
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq1 }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq1
set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq2 }]; #IO_L2P_T0_D02_14 Sch=qspi_dq2
set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq3 }]; #IO_L2N_T0_D03_14 Sch=qspi_dq3

## Configuration options, can be used for all designs
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
## and to be able to use this pin as an ordinary I/O the following property must
## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
## used the internal reference is set to half that value (i.e. 0.675v). Note that
## this property must be set even if SW3 is not used in the design.
set_property INTERNAL_VREF 0.675 [get_iobanks 34]


Plain text
Multisim PLD configuration file
<PLDConfiguration Version="1.0">
    <Component Name="Digilent Arty S7-50" PartNumber="XC7S50" Version="1.0" OpVoltageInput="3.3" OpVoltageOutput="3.3" OpVoltageBidirectional="3.3" BoardId="">
		<DeviceList BoardName="Digilent Arty S7-50">
			<XilinxDevice Manufacturer="Xilinx" Family="Spartan-7" Device="XC7S50" Package="CSGA324" Speed="-1" DeviceOffset="1" DeviceId="" Ucf="Arty-S7-50-Master.xdc" ></XilinxDevice>
			<Interface CableTarget="digilent_plugin"></Interface>
		<Pins Locked="1">

            <Pin Name="CLK12MHZ" Mode="in" Location="left" Place="0" ></Pin>
            <Pin Name="CLK100MHZ" Mode="in" Location="left" Place="0" ></Pin>

            <Pin Name="sw0" Mode="in" Location="left" Place="1" ></Pin>
            <Pin Name="sw1" Mode="in" Location="left" Place="1" ></Pin>
            <Pin Name="sw2" Mode="in" Location="left" Place="1" ></Pin>
            <Pin Name="sw3" Mode="in" Location="left" Place="1" ></Pin>

            <Pin Name="led0_r" Mode="out" Location="right" Place="0" ></Pin>
            <Pin Name="led0_g" Mode="out" Location="right" Place="0" ></Pin>
            <Pin Name="led0_b" Mode="out" Location="right" Place="0" ></Pin>
            <Pin Name="led1_r" Mode="out" Location="right" Place="0" ></Pin>
            <Pin Name="led1_g" Mode="out" Location="right" Place="0" ></Pin>
            <Pin Name="led1_b" Mode="out" Location="right" Place="0" ></Pin>

            <Pin Name="led0" Mode="out" Location="right" Place="1" ></Pin>
            <Pin Name="led1" Mode="out" Location="right" Place="1" ></Pin>
            <Pin Name="led2" Mode="out" Location="right" Place="1" ></Pin>
            <Pin Name="led3" Mode="out" Location="right" Place="1" ></Pin>

            <Pin Name="btn0" Mode="in" Location="left" Place="0" ></Pin>
            <Pin Name="btn1" Mode="in" Location="left" Place="0" ></Pin>
            <Pin Name="btn2" Mode="in" Location="left" Place="0" ></Pin>
            <Pin Name="btn3" Mode="in" Location="left" Place="0" ></Pin>

            <Pin Name="ja0" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ja1" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ja2" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ja3" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ja4" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ja5" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ja6" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ja7" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="jb0" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jb1" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jb2" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jb3" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jb4" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jb5" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jb6" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jb7" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="jc0" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jc1" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jc2" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jc3" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jc4" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jc5" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jc6" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jc7" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="jd0" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jd1" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jd2" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jd3" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jd4" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jd5" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jd6" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="jd7" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="uart_rxd_out" Mode="out" Location="left" Place="0" ></Pin>
            <Pin Name="uart_txd_in" Mode="in" Location="left" Place="0" ></Pin>

            <Pin Name="ck_io0" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io1" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io2" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io3" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io4" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io5" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io6" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io7" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io8" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io9" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="ck_io10_ss" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io11_mosi" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io12_miso" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_io13_sck" Mode="bidir" Location="left" Place="0" ></Pin>


            <Pin Name="vp_in" Mode="in" Location="left" Place="0" ></Pin>
            <Pin Name="vn_in" Mode="in" Location="left" Place="0" ></Pin>


            <Pin Name="ck_a0" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a1" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a2" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a3" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a4" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a5" Mode="bidir" Location="left" Place="0" ></Pin>


            <Pin Name="ck_a6" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a7" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a8" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a9" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a10" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_a11" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="ck_scl" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_sda" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="ck_ioa" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="ck_rst" Mode="bidir" Location="left" Place="0" ></Pin>

            <Pin Name="qspi_cs" Mode="out" Location="left" Place="0" ></Pin>
            <Pin Name="qspi_dq0" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="qspi_dq1" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="qspi_dq2" Mode="bidir" Location="left" Place="0" ></Pin>
            <Pin Name="qspi_dq3" Mode="bidir" Location="left" Place="0" ></Pin>



Álmos Veres-Vitályos

Álmos Veres-Vitályos

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